1. Field of the Invention
Generally, the present disclosure relates to the fabrication of integrated circuits, and, more particularly, to the formation of metallization layers of reduced permittivity by using low-k dielectric materials.
2. Description of the Related Art
In an integrated circuit, a very large number of circuit elements, such as transistors, capacitors, resistors and the like, are formed in or on an appropriate substrate, usually in a substantially planar configuration. Due to the large number of circuit elements and the required complex layout of advanced integrated circuits, the electrical connections of the individual circuit elements are generally not established within the same level on which the circuit elements are manufactured. Typically, such electrical connections are formed in one or more additional “wiring” layers, also referred to as metallization layers. These metallization layers generally include metal-containing lines, providing the inner-level electrical connection, and a plurality of inter-level connections, also referred to as vias, which provide the electrical connection between two neighboring stacked metallization layers, wherein the metal-containing lines and vias may also be commonly referred to as interconnect structures.
Due to the ongoing demand for shrinking the feature sizes of highly sophisticated semiconductor devices, highly conductive metals, such as copper and alloys thereof, in combination with a low-k dielectric material, have become a frequently used alternative in the formation of metallization layers. Typically, a plurality of metallization layers stacked on top of each other is necessary to realize the connections between all internal circuit elements and I/O (input/output), power and ground pads of the circuit design under consideration. For extremely scaled integrated circuits, the signal propagation delay and, thus, the operating speed of the integrated circuit may no longer be limited by the field effect transistors but may be restricted by the close proximity of the metal lines, owing to the increased density of circuit elements, requiring an even more increased number of electrical connections, since the line-to-line capacitance is increased, which is accompanied by the fact that the metal lines have a reduced conductivity due to a reduced cross-sectional area. For this reason, traditional dielectrics, such as silicon dioxide (k>3.6) and silicon nitride (k>5), are replaced by dielectric materials having a lower dielectric constant k, which are therefore also referred to as low-k dielectrics having a relative permittivity of 3.0 or less. The reduced permittivity of these low-k materials is frequently achieved by providing the dielectric material in a porous configuration, thereby offering a k-value of significantly less than 3.0. Due to the intrinsic properties, such as a high degree of porosity, of the dielectric material, however, the density and mechanical stability or strength may be significantly less compared to the well-approved dielectrics silicon dioxide and silicon nitride.
During the formation of copper-based metallization layers, a so-called damascene or inlaid technique is usually used, due to copper's characteristic of substantially not forming volatile etch products when being exposed to well-established anisotropic etch ambients. In addition, copper may also not be deposited with high deposition rates on the basis of well-established deposition techniques usually used for aluminum, such as chemical vapor deposition (CVD). Thus, in the inlaid technique, therefore, the dielectric material is patterned to receive trenches and/or vias, which are subsequently filled with the metal by an efficient electrochemical deposition technique. Moreover, a barrier layer is usually formed on exposed surface portions of the dielectric material prior to filling in the metal, which provides the desired adhesion of the metal to the surrounding dielectric material and also suppresses copper diffusion into sensitive device areas, as copper may readily diffuse in a plurality of dielectric materials, in particular in porous low-k dielectrics.
In some conventional approaches, the process of filling in a conductive metal, such as copper, may be accomplished in a so-called dual damascene strategy, in which the via opening, connecting to an underlying metal region, and a corresponding trench may be filled in a common deposition process, thereby enhancing the overall process efficiency. For this purpose, the via opening and the trench are formed in the dielectric material of the metallization layer under consideration and subsequently the barrier material and the copper material are filled in, wherein each of these processes may be performed commonly for the via opening and the trench. For example, after the deposition of an appropriate dielectric material, for instance a low-k dielectric material, a patterning sequence is performed, wherein, in some illustrative approaches, the via opening may be formed first, at least partially, followed by the patterning of a trench in the upper portion of the dielectric material. Consequently, in this approach, the patterning of the trenches has to be accomplished on the basis of a surface topography including the previously formed via openings or portions thereof, which may be accomplished by planarizing the surface topography prior to lithographically patterning an etch mask for the trench etch process. Thus, during the overall patterning sequence, resist masks, possibly in combination with appropriate planarization materials, which may frequently be provided in the form of organic materials, may have to be deposited and formed above the dielectric material with a subsequent resist removal process, which may increasingly damage the sensitive dielectric material, in particular when highly-scaled semiconductor devices are considered, which may require ultra low dielectric constant, for example based on porous dielectric materials, as will be described in more detail with reference to FIGS. 1a-1d. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 in an advanced manufacturing stage, in which one or more metallization layers are to be formed above a device level of the semiconductor device 100. In the manufacturing stage shown, the semiconductor device 100 comprises a substrate 101, which, for convenience, is to be considered as an appropriate carrier material having formed thereon one or more material layers for receiving semiconductor circuit elements, such as transistors, capacitors, resistors and the like, which for convenience are not shown in FIG. 1a. For example, the substrate 101 may represent a semiconductor material, for instance, a silicon material in combination with an appropriate semiconductor layer, such as a silicon-based layer, in and above which transistor elements may be formed. In other cases, a buried insulating layer (not shown) may be formed between the substrate material and the corresponding semiconductor layer, thereby providing a semiconductor-on-insulator (SOI) configuration. As previously discussed, the circuit elements provided in the device level of the semiconductor device 100 may have critical dimensions of approximately 40 nm and less, depending on the technology standard under consideration.
Above the substrate 101, including the semiconductor circuit elements, a metallization system is provided, which may be represented by a first metallization layer 110 comprised of a dielectric material 111, which may be provided in the form of a conventional dielectric material, such as silicon dioxide, silicon nitride, silicon oxynitride and the like, depending on the overall device and process requirements. In sophisticated applications, the dielectric material 111 may comprise a low-k dielectric material to reduce the overall parasitic capacitance between adjacent metal regions. Furthermore, the metallization layer 110 may comprise a metal region, for instance in the form of a metal line 112, which may include a highly conductive metal, such as copper, in combination with a barrier material 112A, which in turn may include two or more layers, such as tantalum, tantalum nitride and the like, in order to obtain the desired barrier and adhesion effect. For example, tantalum nitride may provide enhanced adhesion to the surrounding dielectric material, while tantalum may provide a superior copper diffusion blocking effect, while also endowing enhanced mechanical stability to the copper material of the metal region 112. Furthermore, the metallization layer 110 may include an etch stop layer 113, which may be comprised of silicon nitride, silicon carbide, nitrogen-containing silicon carbide and the like, wherein the etch stop layer 113 may not only act as an etch stop material during the further processing of the device 100, but may also confine an upper surface of the metal line 112, for instance in view of undue copper diffusion and any interaction of reactive components, such as oxygen, fluorine, with the highly reactive copper material in the metal line 112.
A further metallization layer 120 is provided in an initial stage, that is, a dielectric material 121 is formed above the metallization layer 110 and is comprised of an appropriate material and with a desired thickness so as to receive a via opening and a trench opening in accordance with the design rules in a subsequent manufacturing stage. For instance, in sophisticated applications, the dielectric material 121 may comprise a low-k dielectric material having a reduced density, for instance by creating a porous structure so as to obtain moderately low values for the dielectric constant. Thus, the dielectric material 121 may exhibit a reduced mechanical stability and may also be sensitive to a plurality of etch chemistries which may be frequently applied during the further processing of the device. For this reason, typically, a cap layer 122 may be provided in an attempt to enhance the overall resistivity of the dielectric material 121 with respect to the further processing. For example, the cap layer 122 may be comprised of any appropriate material, for instance silicon dioxide, and the like, or the cap layer 122 may represent a surface portion of the dielectric material 121 having received an appropriate treatment, such as an oxidation process and the like. Furthermore, in the manufacturing stage shown, an etch mask 130 may be formed above the cap layer 122 and may be comprised of one or more resist materials, possibly in combination with other organic materials or other anti-reflective coating (ARC) materials, according to well-established techniques, so as to enable a lithographic patterning of the etch mask 130.
Typically, the device 100 as shown in FIG. 1a may be formed on the basis of well-established process techniques. For example, the circuit elements (not shown) may be formed by using sophisticated process techniques in conformity with design rules in order to obtain feature sizes as required. After forming an appropriate contact structure (not shown), that is, an interlayer dielectric material having a planarized surface topography for enclosing and passivating the circuit elements, including appropriate conductive elements connecting to contact areas of the circuit elements, the one or more metallization layers 110, 120 may be formed. For this purpose, the dielectric material 111 may be deposited and subsequently be patterned to receive vias and/or trenches, followed by the deposition of the barrier material 112A, which may be accomplished by sputter deposition, chemical vapor deposition (CVD) and the like. It should be appreciated that the metallization layer 110 may be formed by similar process techniques, as will be described with reference to the metallization layer 120, depending on the overall process and device requirements. Thereafter, the metal, such as copper, may be filled in, for instance, by electroplating, wherein, prior to the electrochemical deposition process, a conductive seed layer, such as copper and the like, may be formed by appropriate deposition techniques, such as sputter deposition, electroless plating and the like. After filling in the copper material, any excess material thereof may be removed, for instance by electrochemical etching, chemical mechanical polishing (CMP) and the like. Next, the etch stop layer 113 may be formed by depositing one or more appropriate materials, on the basis of well-established CVD techniques. Next, the dielectric material 121 may be formed by any appropriate deposition technique, such as CVD, spin-on processes and the like. Thereafter, the cap layer 122 may be formed, for instance, by oxidizing a surface portion of the dielectric material 121, if the material 121 has an appropriate material composition, or by depositing an appropriate thin material layer so as to not unduly affect the overall permittivity of the dielectric material 121. Finally, the etch mask 130 may be formed by depositing a resist material, possibly in combination with appropriate ARC materials and the like and performing a lithography process to form an opening 130A that substantially corresponds to a via opening to be formed in the dielectric material 121. Based on the etch mask 130, an etch process 131 is performed for etching through the material 121, wherein the corresponding etch process is stopped on and in the etch stop layer 113. Subsequently, the etch mask 130 is removed, for instance by resist stripping processes including oxygen plasma based recipes, possibly in combination with reactive components such as fluorine, which may be present in the etch chamber due to the previously performed etch steps, which may result in a more or less pronounced material removal of the cap layer 122 and possibly of the sensitive dielectric material 121.
FIG. 1b schematically illustrates the semiconductor device 100 after the above-described process sequence. Hence, the cap layer 122 and possibly a surface area of the dielectric material 121 may exhibit a certain degree of etch damage 122A caused by the previous etch processes for removing the etch mask 130.
FIG. 1c schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage, in which a planarization material 132, for instance in the form of an organic material, may be formed in the via opening 121A and above the dielectric material 121 and the cap layer 122. As previously explained, the planarization material 132 may provide a substantially planarized surface topography and may also act as an ARC material during the lithography process for patterning a further etch mask 133, which may be provided in the form of a resist material and the like. The planarization layer 132 may be formed by depositing an appropriate material in a low viscous state by spin-on techniques and subsequently hardening the material 132. Thereafter, an appropriate resist material may be deposited and may be patterned to form a trench opening 133A, which may be used as an etch mask during an etch process 134. During the etch process 134, the planarization layer 132 may be patterned first and subsequently the material of the layer 121 may be removed so as to form a trench therein. Thereafter, the mask 133 and the planarization material 132 may be removed, for instance, by well-established plasma strip recipes, during which, however, the dielectric material 121 and cap layer 122 may be exposed to the corresponding reactive ambient.
FIG. 1d schematically illustrates the semiconductor device 100 after the above-described process sequence, wherein a trench 121T may be formed in an upper portion of the dielectric material 121, which, however, may comprise significant damage at a surface 122B thereof, due to the preceding plasma-based processes for removing the etch mask 133 and the planarization layer 132. Consequently, in particular in highly scaled semiconductor devices, significant surface irregularities may be created in the dielectric materials of respective metallization layers, thereby providing non-uniform process conditions during the further processing of the devices, for instance in view of subsequent deposition techniques for forming a barrier material and a highly conductive metal in combination with subsequent planarization processes, wherein the highly irregular surface conditions of the dielectric material 121 may also have a negative impact on the finally obtained device characteristics.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.